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wide supply range, rail-to-rail output instrumentation amplifier ad8426 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features 2 channels in a small, 4 mm 4 mm lfcsp lfcsp package has no metal pad more routing room no current leakage to pad gain set with 1 external resistor gain range: 1 to 1000 input voltage goes below ground inputs protected beyond supplies very wide power supply range single supply: 2.2 v to 36 v dual supply: 1.35 v to 18 v bandwidth (g = 1): 1 mhz cmrr (g = 1): 80 db minimum input noise: 24 nv/hz typical supply current (per amplifier): 350 a specified temperature range: ?40c to +125c applications industrial process controls bridge amplifiers medical instrumentation portable data acquisition multichannel systems connection diagram 1 2 3 4 12 11 10 9 5678 13141516 ?in1 +in1 rg1 rg1 ad8426 +v s out1 out2 ?v s ?in2 +in2 rg2 rg2 09490-001 +v s ?v s ref1 ref2 figure 1. table 1. instrumentation amplifiers by category 1 general- purpose zero drift military grade low power high speed pga ad8220 ad8231 ad620 ad627 ad8250 ad8221 ad8290 ad621 ad623 ad8251 ad8222 ad8293 ad524 ad8235 ad8253 ad8224 ad8553 ad526 ad8236 ad8228 ad8556 ad624 ad8426 ad8295 ad8557 ad8226 ad8227 1 see www.analog.com for the latest instrumentation amplifiers. general description the ad8426 is a dual-channel, low cost, wide supply range instrumentation amplifier that requires only one external resistor to set any gain from 1 to 1000. the ad8426 is designed to work with a variety of signal voltages. a wide input range and rail-to-rail output allow the signal to make full use of the supply rails. because the input range can also go below the negative supply, small signals near ground can be amplified without requiring dual supplies. the ad8426 operates on supplies ranging from 1.35 v to 18 v for dual supplies and 2.2 v to 36 v for a single supply. the robust ad8426 inputs are designed to connect to real- world sensors. in addition to its wide operating range, the ad8426 can handle voltages beyond the rails. for example, with a 5 v supply, the part is guaranteed to withstand 35 v at the input with no damage. minimum and maximum input bias currents are specified to facilitate open-wire detection. the ad8426 is designed to make pcb routing easy and efficient. the two amplifiers are arranged in a logical way so that typical application circuits have short routes and few vias. unlike most chip scale packages, the ad8426 does not have an exposed metal pad on the bottom of the part, which frees additional space for routing and vias. the ad8426 offers two in-amps in the equivalent board space of a typical msop package. the ad8426 is ideal for multichannel, space-constrained industrial applications. unlike other low cost, low power instrumentation amplifiers, the ad8426 is designed with a minimum gain of 1 and can easily handle 10 v signals. with its space-saving lfcsp package and 125c temperature rating, the ad8426 thrives in tightly packed, zero airflow designs. the ad8226 is the single-channel version of the ad8426.
ad8426 rev. 0 | page 2 of 28 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? connection diagram ....................................................................... 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? dual-supply operation ............................................................... 3 ? single-supply operation ............................................................. 6 ? absolute maximum ratings ............................................................ 9 ? thermal resistance ...................................................................... 9 ? esd caution .................................................................................. 9 ? pin configuration and function descriptions ........................... 10 ? typical performance characteristics ........................................... 11 ? theory of operation ...................................................................... 21 ? architecture ................................................................................. 21 ? gain selection ............................................................................. 21 ? reference terminal .................................................................... 22 ? input voltage range ................................................................... 22 ? layout .......................................................................................... 23 ? input bias current return path ............................................... 24 ? input protection ......................................................................... 24 ? radio frequency interference (rfi) ........................................ 24 ? applications information .............................................................. 25 ? precision strain gage ................................................................. 25 ? differential drive ....................................................................... 25 ? driving a cable ........................................................................... 26 ? driving an adc ......................................................................... 27 ? outline dimensions ....................................................................... 28 ? ordering guide .......................................................................... 28 ? revision history 7/11revision 0: initial version
ad8426 rev. 0 | page 3 of 28 specifications dual-supply operation +v s = +15 v, ?v s = ?15 v, v ref = 0 v, t a = 25c, g = 1, r l = 10 k, specifications referred to input, unless otherwise noted. table 2. test conditions/ comments a grade b grade parameter min typ max min typ max unit common-mode rejection ratio (cmrr) v cm = ?10 v to +10 v cmrr, dc to 60 hz g = 1 80 90 db g = 10 100 105 db g = 100 105 110 db g = 1000 105 110 db cmrr at 5 khz g = 1 80 80 db g = 10 90 90 db g = 100 90 90 db g = 1000 100 100 db noise total noise: e n = (e ni 2 + (e no /g) 2 ) voltage noise f = 1 khz input voltage noise, e ni 24 27 24 27 nv/hz output voltage noise, e no 120 125 120 125 nv/hz rti noise f = 0.1 hz to 10 hz g = 1 2 2 v p-p g = 10 0.5 0.5 v p-p g = 100 to 1000 0.4 0.4 v p-p current noise f = 1 khz 100 100 fa/hz f = 0.1 hz to 10 hz 3 3 pa p-p voltage offset total offset voltage: v os = v osi + (v oso /g) input offset, v osi v s = 5 v to 15 v 200 100 v average temperature coefficient t a = ?40c to +125c 0.5 2 0.5 1 v/c output offset, v oso v s = 5 v to 15 v 1000 500 v average temperature coefficient t a = ?40c to +125c 2 10 1 5 v/c offset rti vs. supply (psr) v s = 5 v to 15 v g = 1 80 90 db g = 10 100 105 db g = 100 105 110 db g = 1000 105 110 db input current input bias current 1 t a = +25c 5 20 27 5 20 27 na t a = +125c 5 15 25 5 15 25 na t a = ?40c 5 30 35 5 30 35 na average temperature coefficient t a = ?40c to +125c 70 70 pa/c input offset current t a = +25c 1.5 0.5 na t a = +125c 1.5 0.5 na t a = ?40c 2 0.5 na average temperature coefficient t a = ?40c to +125c 5 5 pa/c
ad8426 rev. 0 | page 4 of 28 test conditions/ comments a grade b grade parameter min typ max min typ max unit reference input r in 100 100 k i in 7 7 a voltage range ?v s +v s ?v s +v s v reference gain to output 1 1 v/v reference gain error 0.01 0.01 % gain g = 1 + (49.4 k/r g ) gain range 1 1000 1 1000 v/v gain error v out 10 v g = 1 0.04 0.01 % g = 5 to 1000 0.3 0.1 % gain nonlinearity v out = ?10 v to +10 v g = 1 to 10 r l 2 k 20 20 ppm g = 100 r l 2 k 75 75 ppm g = 1000 r l 2 k 750 750 ppm gain vs. temperature 2 g = 1 t a = ?40c to +85c 5 1 ppm/c t a = +85c to +125c 5 2 ppm/c g > 1 t a = ?40c to +125c ?100 ?100 ppm/c input v s = 1.35 v to +36 v input impedance differential 0.8||2 0.8||2 g||pf common mode 0.4||2 0.4||2 g||pf input operating voltage range 3 t a = +25c ?v s ? 0.1 +v s ? 0.8 ?v s ? 0.1 +v s ? 0.8 v t a = +125c ?v s ? 0.05 +v s ? 0.6 ?v s ? 0.05 +v s ? 0.6 v t a = ?40c ?v s ? 0.15 +v s ? 0.9 ?v s ? 0.15 +v s ? 0.9 v input overvoltage range t a = ?40c to +125c +v s ? 40 ?v s + 40 +v s ? 40 ?v s + 40 v output output swing r l = 2 k to ground t a = +25c ?v s + 0.4 +v s ? 0.7 ?v s + 0.4 +v s ? 0.7 v t a = +125c ?v s + 0.4 +v s ? 1.0 ?v s + 0.4 +v s ? 1.0 v t a = ?40c ?v s + 1.2 +v s ? 1.1 ?v s + 1.2 +v s ? 1.1 v r l = 10 k to ground t a = +25c ?v s + 0.2 +v s ? 0.2 ?v s + 0.2 +v s ? 0.2 v t a = +125c ?v s + 0.3 +v s ? 0.3 ?v s + 0.3 +v s ? 0.3 v t a = ?40c ?v s + 0.2 +v s ? 0.2 ?v s + 0.2 +v s ? 0.2 v r l = 100 k to ground t a = ?40c to +125c ?v s + 0.1 +v s ? 0.1 ?v s + 0.1 +v s ? 0.1 v short-circuit current 13 13 ma power supply operating range dual-supply operation 1.35 18 1.35 18 v quiescent current (per amplifier) t a = +25c 350 425 350 425 a t a = ?40c 250 325 250 325 a t a = +85c 450 525 450 525 a t a = +125c 525 600 525 600 a temperature range ?40 +125 ?40 +125 c 1 the input stage uses pnp transi stors; therefore, input bias curre nt always flows into the part. 2 the values specified for g > 1 do not include the effects of the external gain-setting resistor, r g . 3 input voltage range of the ad8426 input stage. the input range depends on the common-mode voltage, the differential voltage, the gain, and the reference voltage . see the se ction for more information. input voltage range
ad8426 rev. 0 | page 5 of 28 dynamic performance specifications +v s = +15 v, ?v s = ?15 v, v ref = 0 v, t a = 25c, g = 1, r l = 10 k, specifications referred to input, unless otherwise noted. table 3. single-ended output configuration (both amplifiers) test conditions/ comments a grade b grade parameter min typ max min typ max unit dynamic response small signal ?3 db bandwidth g = 1 1000 1000 khz g = 10 160 160 khz g = 100 20 20 khz g = 1000 2 2 khz settling time 0.01% 10 v step g = 1 25 25 s g = 10 15 15 s g = 100 40 40 s g = 1000 750 750 s slew rate g = 1 0.4 0.4 v/s g = 5 to 100 0.6 0.6 v/s table 4. differential output configuration test conditions/ comments a grade b grade parameter min typ max min typ max unit dynamic response small signal ?3 db bandwidth g = 1 850 850 khz g = 10 300 300 khz g = 100 30 30 khz g = 1000 2 2 khz settling time 0.01% 10 v step g = 1 25 25 s g = 10 15 15 s g = 100 80 80 s g = 1000 300 300 s slew rate g = 1 0.4 0.4 v/s g = 5 to 100 0.6 0.6 v/s
ad8426 rev. 0 | page 6 of 28 single-supply operation +v s = 2.7 v, ?v s = 0 v, v ref = 0 v, t a = 25c, g = 1, r l = 10 k, specifications referred to input, unless otherwise noted. table 5. test conditions/ comments a grade b grade parameter min typ max min typ max unit common-mode rejection ratio (cmrr) v cm = 0 v to 1.7 v cmrr, dc to 60 hz g = 1 80 90 db g = 10 100 105 db g = 100 105 110 db g = 1000 105 110 db cmrr at 5 khz g = 1 80 80 db g = 10 90 90 db g = 100 90 90 db g = 1000 100 100 db noise total noise: e n = (e ni 2 + (e no /g) 2 ) voltage noise f = 1 khz input voltage noise, e ni 24 27 24 27 nv/hz output voltage noise, e no 120 125 120 125 nv/hz rti noise f = 0.1 hz to 10 hz g = 1 2 2 v p-p g = 10 0.5 0.5 v p-p g = 100 to 1000 0.4 0.4 v p-p current noise f = 1 khz 100 100 fa/hz f = 0.1 hz to 10 hz 3 3 pa p-p voltage offset total offset voltage: v os = v osi + (v oso /g) input offset, v osi 300 150 v average temperature coefficient t a = ?40c to +125c 0.5 3 0.5 1.5 v/c output offset, v oso 1000 500 v average temperature coefficient t a = ?40c to +125c 2 12 1 8 v/c offset rti vs. supply (psr) v s = 2.7 v to 36 v g = 1 80 90 db g = 10 100 105 db g = 100 105 110 db g = 1000 105 110 db input current input bias current 1 t a = +25c 5 20 30 5 20 30 na t a = +125c 5 15 28 5 15 28 na t a = ?40c 5 30 38 5 30 38 na average temperature coefficient t a = ?40c to +125c 70 70 pa/c input offset current t a = +25c 2 1 na t a = +125c 2 1 na t a = ?40c 3 1 na average temperature coefficient t a = ?40c to +125c 5 5 pa/c
ad8426 rev. 0 | page 7 of 28 test conditions/ comments a grade b grade parameter min typ max min typ max unit reference input r in 100 100 k i in 7 7 a voltage range ?v s +v s ?v s +v s v reference gain to output 1 1 v/v reference gain error 0.01 0.01 % gain g = 1 + (49.4 k/r g ) gain range 1 1000 1 1000 v/v gain error g = 1 v out = 0.8 v to 1.8 v 0.05 0.05 % g = 5 to 1000 v out = 0.2 v to 2.5 v 0.3 0.1 % gain vs. temperature 2 g = 1 t a = ?40c to +85c 5 1 ppm/c t a = +85c to +125c 5 2 ppm/c g > 1 t a = ?40c to +125c ?100 ?100 ppm/c input ?v s = 0 v, +v s = 2.7 v to 36 v input impedance differential 0.8||2 0.8||2 g||pf common mode 0.4||2 0.4||2 g||pf input operating voltage range 3 t a = +25c ?0.1 +v s ? 0.7 ?0.1 +v s ? 0.7 v t a = +125c ?0.05 +v s ? 0.6 ?0.05 +v s ? 0.6 v t a = ?40c ?0.15 +v s ? 0.9 ?0.15 +v s ? 0.9 v input overvoltage range t a = ?40c to +125c +v s ? 40 ?v s + 40 +v s ? 40 ?v s + 40 v output output swing r l = 10 k to 1.35 v t a = ?40c to +125c 0.1 +v s ? 0.1 0.1 +v s ? 0.1 v short-circuit current 13 13 ma power supply operating range single-supply operation 2.2 36 2.2 36 v quiescent current (per amplifier) ?v s = 0 v, +v s = 2.7 v t a = +25c 325 400 325 400 a t a = ?40c 250 325 250 325 a t a = +85c 425 500 425 500 a t a = +125c 475 550 475 550 a temperature range ?40 +125 ?40 +125 c 1 the input stage uses pnp transi stors; therefore, input bias curre nt always flows into the part. 2 the values specified for g > 1 do not include the effects of the external gain-setting resistor, r g . 3 input voltage range of the ad8426 input stage. the input range depends on the common-mode voltage, the differential voltage, the gain, and the reference voltage . see the se ction for more information. input voltage range
ad8426 rev. 0 | page 8 of 28 dynamic performance specifications +v s = 2.7 v, ?v s = 0 v, v ref = 0 v, t a = 25c, g = 1, r l = 10 k, specifications referred to input, unless otherwise noted. table 6. single-ended output configuration (both amplifiers) test conditions/ comments a grade b grade parameter min typ max min typ max unit dynamic response small signal ?3 db bandwidth g = 1 1000 1000 khz g = 10 160 160 khz g = 100 20 20 khz g = 1000 2 2 khz settling time 0.01% 2 v step g = 1 6 6 s g = 10 6 6 s g = 100 35 35 s g = 1000 750 750 s slew rate g = 1 0.4 0.4 v/s g = 5 to 100 0.6 0.6 v/s table 7. differential output configuration test conditions/ comments a grade b grade parameter min typ max min typ max unit dynamic response small signal ?3 db bandwidth g = 1 850 850 khz g = 10 300 300 khz g = 100 30 30 khz g = 1000 2 2 khz settling time 0.01% 2 v step g = 1 25 25 s g = 10 15 15 s g = 100 80 80 s g = 1000 300 300 s slew rate g = 1 0.4 0.4 v/s g = 5 to 100 0.6 0.6 v/s
ad8426 rev. 0 | page 9 of 28 absolute maximum ratings thermal resistance table 8. parameter rating supply voltage 18 v output short-circuit current indefinite maximum voltage at ?inx or +inx ?v s + 40 v minimum voltage at ?inx or +inx +v s ? 40 v refx voltage v s storage temperature range ?65c to +150c specified temperature range ?40c to +125c maximum junction temperature 130c esd human body model 1.5 kv charged device model 1.5 kv machine model 100 v the ja value in table 9 assumes a 4-layer jedec standard board with zero airflow. table 9. package ja unit 16-lead lfcsp (cp-16-19) 86 c/w esd caution stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ad8426 rev. 0 | page 10 of 28 pin configuration and fu nction descriptions 1 2 3 4 12 11 10 9 5678 13141516 ?in1 +in1 rg1 rg1 ad8426 +v s out1 out2 ?v s ?in2 +in2 rg2 rg2 09490-002 +v s ?v s ref1 ref2 figure 2. pin configuration table 10. pin function descriptions pin no. mnemonic description 1 ?in1 negative input, in-amp 1 2 rg1 gain-setting resistor terminal, in-amp 1 3 rg1 gain-setting resistor terminal, in-amp 1 4 +in1 positive input, in-amp 1 5 +v s positive supply 6 ref1 reference adjust, in-amp 1 7 ref2 reference adjust, in-amp 2 8 ?v s negative supply 9 +in2 positive input, in-amp 2 10 rg2 gain-setting resistor terminal, in-amp 2 11 rg2 gain-setting resistor terminal, in-amp 2 12 ?in2 negative input, in-amp 2 13 ?v s negative supply 14 out2 output, in-amp 2 15 out1 output, in-amp 1 16 +v s positive supply
ad8426 rev. 0 | page 11 of 28 typical performance characteristics t a = 25c, v s = 15 v, r l = 10 k, unless otherwise noted. 60 0 10 20 30 40 50 ?100 100 50 0 ?50 hits cmrr (v/v) in-amp 1 in-amp 2 09490-303 figure 3. typical distribution for cmrr (g = 1) 0 10 20 30 40 50 ?100 100 50 0 ?50 hits v osi (v) in-amp 1 in-amp 2 09490-304 figure 4. typical distributi on of input offset voltage 0 10 20 30 40 60 50 ?600 600 200 400 0 ?200 ?400 hits in-amp 1 in-amp 2 09490-305 v oso (v) figure 5. typical distribution of output offset voltage 0 10 20 30 40 ?21 ?20 ?19 ?18 ?17 hits i bias (na) in-amp 1 in-amp 2 09490-306 figure 6. typical distribution of input bias current, inverting input 0 10 20 30 40 50 ?21 ?20 ?19 ?18 ?17 hits i bias (na) in-amp 1 in-amp 2 09490-307 figure 7. typical distribution of in put bias current, noninverting input 0 10 20 30 50 70 40 60 ?0.010 ?0.005 0 0.005 0.010 hits gain error (%) in-amp 1 in-amp 2 09490-308 figure 8. typical distribution of gain error (g = 1)
ad8426 rev. 0 | page 12 of 28 +0.01v, +1.90v 0.00v, ?0.45v +2.17v, +0.90v +1.35v, +1.95v +0.01v, +1.28v +0.01v, +0.31v +1.35v, ?0.41v +2.61v, +0.37v +2.61v, +1.13v ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 input common-mode voltage (v) output voltage (v) v ref = 0v v ref = +1.35v 09490-103 figure 9. input common-mode voltage vs. output voltage, single supply, v s = 2.7 v, g = 1 +0.02v, +4.25v +0.01v, ?0.30v +4.64v, +2.03v +2.50v, +4.25v +0.02v, +2.95v +0.01v, +0.87v +2.50v, ?0.40v +4.90v, +0.82v +4.90v, +3.03v ?1 0 1 2 3 4 5 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 6.05.55.0 input common-mode voltage (v) output voltage (v) v ref = 0v v ref = +2.5v 09490-104 figure 10. input common-mode voltage vs. output voltage, single supply, v s = 5 v, g = 1 0v, +4.25v ?4.93v, +1.77v ?4.93v, ?2.83v 0v, ?5.30v +4.90v, ?2.84v +4.87v, +1.79v ?6 ?4 ?2 0 2 4 6 ?6 ?4 ?2 0 2 4 6 output voltage (v) input common-mode voltage (v) 09490-105 figure 11. input common-mode voltage vs. output voltage, dual supply, v s = 5 v, g = 1 +0.01v, +1.90v +0.01v, ?0.40v +2.46v, +0.72v +1.35v, +1.94v +0.01v, +1.19v +0.01v, +0.05v +1.35v, ?0.55v +2.61v, +0.08v +2.60v, +1.11v ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 input common-mode voltage (v) output voltage (v) v ref = 0v v ref = +1.35v 09490-106 figure 12. input common-mode voltage vs. output voltage, single supply, v s = 2.7 v, g = 100 +0.02v, +4.20v +0.01v, ?0.40v +4.77v, +1.71v +2.49v, +4.25v +0.02v, +2.89v +0.01v, +0.69v +2.49v, ?0.30v +4.90v, +0.54v +4.90v, +3.02v ?1 0 1 2 3 4 5 ?0.5 0 0.5 1.0 2.0 3.0 4.0 5.55.0 1.52.53.54.5 input common-mode voltage (v) output voltage (v) v ref = 0v v ref = +2.50v 09490-107 figure 13. input common-mode voltage vs. output voltage, single supply, v s = 5 v, g = 100 0v, +4.24v ?4.93v, +1.74v ?4.93v, ?3.15v ?0.01v, ?5.30v +4.90v, ?3.18v +4.90v, +1.76v ?6 ?4 ?2 0 2 4 6 ?6 ?4 ?2 0 2 4 6 output voltage (v) input common-mode voltage (v) 09490-108 figure 14. input common-mode voltage vs. output voltage, dual supply, v s = 5 v, g = 100
ad8426 rev. 0 | page 13 of 28 20 ?20 ?15 ?10 ?5 0 5 10 15 ?20 ?15 ?10 ?5 0 5 10 15 20 input common-mode voltage (v) output voltage (v) 0v, ?15.3v 0v, ?12.3v +11.8v, ?6.5v +14.8v, ?7.9v +14.8v, +6.8v +11.9v, +5.3v 0v, +14.2v 0v, +11.2v ?11.9v, +5.2v ?14.9v, +6.7v ?14.9v, ?7.6v ?11.9v, ?6.0v v s = 15v v s = 12v 09490-109 figure 15. input common-mode voltage vs. output voltage, dual supply, v s = 15 v and v s = 12 v, g = 1 2.75 ?0.25 0.6 ?0.6 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 30 35 40 output voltage (v) input current (ma) input voltage (v) v s = 2.7v g = 1 ?v in = 0v v out i in 09490-110 figure 16. input overvoltage performance, single supply, v s = 2.7 v, g = 1 16 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 12 14 0.6 0.7 0.8 ?0.6 ?0.7 ?0.8 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 30 35 40 output voltage (v) input current (ma) input voltage (v) v s = 15v g = 1 ?v in = 0v v out i in 09490-111 figure 17. input overvoltage performance, dual supply, v s = 15 v, g = 1 20 ?20 ?15 ?10 ?5 0 5 10 15 ?20 ?15 ?10 ?5 0 5 10 15 20 input common-mode voltage (v) output voltage (v) ?0.01v, ?15.3v ?0.01v, ?12.3v +11.8v, ?6.63v +14.8v, ?8.18v +14.8v, +6.64v +11.8v, +5.25v 0v, +14.1v 0v, +11.2v ?11.9v, +5.22v ?14.9v, +6.61v ?14.9v, ?8.09v ?11.9v, ?6.71v v s = 15v v s = 12v 09490-112 figure 18. input common-mode voltage vs. output voltage, dual supply, v s = 15 v and v s = 12 v, g = 100 2.75 ?0.25 0.6 ?0.6 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 30 35 40 output voltage (v) input current (ma) input voltage (v) v s = 2.7v g = 100 ?v in = 0v v out i in 09490-113 figure 19. input overvoltage performance, single supply, v s = 2.7 v, g = 100 16 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 12 14 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 30 35 40 output voltage (v) input current (ma) input voltage (v) v s = 15v g = 100 ?v in = 0v 09490-114 0.6 0.7 0.8 ?0.6 ?0.7 ?0.8 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 v out i in figure 20. input overvoltage performance, dual supply, v s = 15 v, g = 100
ad8426 rev. 0 | page 14 of 28 30 16 18 20 22 24 26 28 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 input bias current (na) common-mode voltage (v) ?0.12v +4.22v 09490-115 figure 21. input bias current vs. common-mode voltage, single supply, v s = 5 v 160 140 120 100 80 60 40 20 0 0.1 1 10 100 1k 10k 100k 1m frequency (hz) positive psrr (db) gain = 1000 gain = 100 gain = 10 gain = 1 09490-322 figure 22. positive psrr vs. frequency, rti 70 60 50 ?30 ?20 ?10 0 10 20 30 40 100 1k 10k 100k 1m 10m frequency (hz) gain (db) gain = 1000 gain = 100 gain = 10 gain = 1 v s = 15v 09490-323 figure 23. gain vs. frequency, dual supply, v s = 15 v 50 ?5 0 5 10 15 20 25 30 35 40 45 ?16 ?12 ?8 ?4 0 4 8 12 16 input bias current (na) common-mode voltage (v) ?15.1v +14.1v 09490-118 figure 24. input bias current vs. common-mode voltage, dual supply, v s = 15 v 160 140 120 100 80 60 40 20 0 0.1 1 10 100 1k 10k 100k 1m frequency (hz) ne g a tive psrr (db) gain = 1000 gain = 100 gain = 10 gain = 1 09490-325 figure 25. negative psrr vs. frequency 70 60 50 ?20 ?10 0 10 20 30 40 100 1k 10k 100k 1m 10m frequency (hz) gain (db) gain = 1000 gain = 100 gain = 10 gain = 1 09490-326 figure 26. gain vs. frequency, single supply, v s = 2.7 v
ad8426 rev. 0 | page 15 of 28 160 140 120 100 80 60 40 20 0 0.1 1 10 100 1k 10k 100k frequency (hz) cmrr (db) gain = 1000 gain = 100 gain = 10 gain = 1 bandwidth limited 09490-327 figure 27. cmrr vs. frequency, rti 120 100 80 60 40 20 0 0.1 1 10 100 1k 10k 100k frequency (hz) cmrr (db) gain = 1000 gain = 1 gain = 100 gain = 10 bandwidth limited 09490-328 figure 28. cmrr vs. frequency, rti, 1 k source imbalance 6 4 2 0 ?2 ?4 5 3 1 ?1 ?3 ?5 ?6 0 20 40 60 80 100 10 30 50 70 90 110 120 warm-up time (seconds) change in input offset voltage (v) 09490-329 figure 29. change in input o ffset voltage vs. warm-up time 0 30 25 20 15 10 5 ?50 250 200 150 100 50 0 ?45 ?25 ?5 15 35 55 75 95 115 135 input bias current (na) input offset current (pa) temperature (c) i os i b 09490-330 figure 30. input bias current and input offset current vs. temperature 40 ?80 ?60 ?40 ?20 0 20 ?60 ?40 ?20 0 20 40 60 100 140 80 120 gain error (v/v) temperature (c) normalized at 25c 09490-125 figure 31. gain error vs. temperature, g = 1 10 ?20 ?15 ?10 ?5 0 5 ?60 ?40 ?20 0 20 40 60 100 140 80 120 cmrr (v/v) temperature (c) representative data normalized at 25c 09490-126 figure 32. cmrr vs. temperature, g = 1
ad8426 rev. 0 | page 16 of 28 + v s ?0.2 ?0.4 ?0.6 ?0.8 ?v s ?0.2 ?0.4 ?0.6 ?0.8 2 4 6 8 10 12 14 16 18 supply voltage (v s ) input voltage (v) referred to supply voltages ?40c +25c +85c +105c +125c 09490-333 figure 33. input voltage limit vs. supply voltage + v s ?0.1 ?0.2 ?0.3 ?0.4 ?v s +0.3 +0.2 +0.1 +0.4 2 4 6 8 10 12 14 16 18 supply voltage (v s ) output voltage swing (v) referred to supply voltages ?40c +25c +85c +105c +125c 09490-334 figure 34. output voltage swing vs. supply voltage, r l = 10 k + v s ?0.8 ?1.0 ?1.2 ?0.2 ?0.4 ?0.6 ?v s +0.4 +0.2 +1.0 +0.8 +0.6 +1.2 2 4 6 8 10 12 14 16 18 supply voltage (v s ) output voltage swing (v) referred to supply voltages ?40c +25c +85c +105c +125c 09490-335 figure 35. output voltage swing vs. supply voltage, r l = 2 k 15 ?15 ?10 ?5 0 5 10 100 1k 100k 10k output voltage swing (v) load resistance ( ? ) ?40c +25c +85c +105c +125c 09490-130 figure 36. output voltage swing vs. load resistance + v s ?0.2 ?0.4 ?0.6 ?0.8 +0.8 +0.6 +0.4 +0.2 ?v s 0.01 0.1 10 1 output voltage swing (v) referred to supply voltages output current (a) ?40c +25c +85c +105c +125c 09490-131 figure 37. output voltage swing vs. output current, g = 1 output voltage (v) linearity (10ppm/div) 09490-338 figure 38. gain nonlinearity, r l 10 k, g = 1
ad8426 rev. 0 | page 17 of 28 output voltage (v) linearity (10ppm/div) 09490-339 figure 39. gain nonlinearity, r l 10 k, g = 10 output voltage (v) linearity (10ppm/div) 09490-340 figure 40. gain nonlinearity, r l 10 k, g = 100 09490-341 output voltage (v) linearity (100ppm/div) figure 41. gain nonlinearity, r l 10 k, g = 1000 10 100 1k 1 100k 1k 10k 100 10 noise (nv/ hz) frequency (hz) gain = 1000 gain = 100 gain = 10 gain = 1 09490-342 figure 42. voltage noise spectral density vs. frequency 1s/div gain = 1000, 200nv/div gain = 1, 1v/div 09490-343 figure 43. 0.1 hz to 10 hz rti voltage noise, g = 1, g = 1000 1k 100 10 1 10 100 1k 10k frequency (hz) noise (fa/ hz) 09490-344 figure 44. current noise spectral density vs. frequency
ad8426 rev. 0 | page 18 of 28 1.5pa/div 1s/div 09490-345 figure 45. 0.1 hz to 10 hz current noise 0 3 6 9 12 15 18 21 24 27 30 100 1k 10k 100k 1m output voltage (v p-p) frequency (hz) v s = 15v v s = +5v 09490-346 figure 46. large signal frequency response 5v/div 26s to 0.01% 27s to 0.001% 0.002%/div 50s/div 09490-347 figure 47. large signal pulse response and settling time, 10 v step, dual supply, v s = 15 v, g = 1 5v/div 17s to 0.01% 23s to 0.001% 0.002%/div 50s/div 09490-348 figure 48. large signal pulse response and settling time, 10 v step, dual supply, v s = 15 v, g = 10 5v/div 42s to 0.01% 60s to 0.001% 0.002%/div 100s/div 09490-349 figure 49. large signal pulse response and settling time, 10 v step, dual supply, v s = 15 v, g = 100 5v/div 580s to 0.01% 780s to 0.001% 0.002%/div 500s/div 09490-350 figure 50. large signal pulse response and settling time, 10 v step, dual supply, v s = 15 v, g = 1000
ad8426 rev. 0 | page 19 of 28 20mv/div 4s/div 09490-145 figure 51. small signal pulse response, r l = 10 k, c l = 100 pf, g = 1 20mv/div 4s/div 09490-146 figure 52. small signal pulse response, r l = 10 k, c l = 100 pf, g = 10 20mv/div 20s/div 09490-147 figure 53. small signal pulse response, r l = 10 k, c l = 100 pf, g = 100 20mv/div 100s/div 09490-148 figure 54. small signal pulse response, r l = 10 k, c l = 100 pf, g = 1000 20mv/div 4s/div no load 47pf 100pf 147pf 09490-149 figure 55. small signal pulse response with various capacitive loads, g = 1, r l = infinity 60 50 40 30 20 10 0 2468101214161820 step size (v) settling time (s) settled to 0.01% settled to 0.001% 09490-356 figure 56. settling time vs. step size, dual supply, v s = 15 v
ad8426 rev. 0 | page 20 of 28 1 8 6 4 760 740 720 700 680 660 640 620 06 12 41 10 21 8 supply current (a) supply voltage (v s ) 09490-151 figure 57. supply current vs. supply voltage (both amplifiers) 0 20 40 60 80 100 120 140 160 180 200 100 1m 10k 100k 1k channel sepa r a tion (db) frequency (hz) gain = 1 gain = 1000 09490-358 figure 58. channel separation vs. frequency, r l = 2 k, source channel at g = 1 and g = 1000 ?20 ?10 0 10 20 30 40 50 60 70 100 1m 10k 100k 1k gain (db) frequency (hz) gain = 1 gain = 10 gain = 100 gain = 1000 09490-359 figure 59. gain vs. frequency, differential output configuration 100 90 80 70 60 50 40 30 20 10 0 1 10 100 1k 10k 100k 1m 10m frequency (hz) output balance (db) limited by measurement system 09490-360 figure 60. output balanc e vs. frequency, differential output configuration
ad8426 rev. 0 | page 21 of 28 theory of operation a3 r2 24.7k ? r1 24.7k ? a1 a2 q2 q1 ?in +in +v s ?v s r3 50k? r4 50k? r5 50k? r b r b +v s ?v s v out ref node 1 node 2 r g v bias + v s ?v s +v s ?v s node 4 node 3 r6 50k? difference amplifier stage gain stage esd and overvoltage protection esd and overvoltage protection ?v s 0 9490-003 figure 61. simplified schematic architecture the ad8426 is based on the classic 3-op-amp topology. this topology has two stages: a gain stage (preamplifier) to provide differential amplification, followed by a difference amplifier stage to remove the common-mode voltage. figure 61 shows a simplified schematic of one of the instrumentation amplifiers in the ad8426 . the first stage works as follows. to maintain a constant voltage across the bias resistor, r b , a1 must keep node 3 at a constant diode drop above the positive input voltage. similarly, a2 keeps node 4 at a constant diode drop above the negative input voltage. therefore, a replica of the differential input voltage is placed across the gain setting resistor, r g . the current that flows across this resistance must also flow through the r1 and r2 resistors, creating a gained differential signal between the a2 and a1 out- puts. note that, in addition to a gained differential signal, the original common-mode signal, shifted up by a diode drop, is also still present. the second stage is a difference amplifier, composed of a3 and four 50 k resistors. the purpose of this stage is to remove the common-mode signal from the amplified differential signal. the transfer function of the ad8426 is v out = g ( v in+ ? v in? ) + v ref where: g r g k 49.4 1 += gain selection placing a resistor across the r g terminals sets the gain of the ad8426 . the gain can be calculated by referring to table 11 or by using the following gain equation: 1 k 49.4 ? = g r g table 11. gains achieved using 1 resistors 1% standard table value of r g calculated gain 49.9 k 1.990 12.4 k 4.984 5.49 k 9.998 2.61 k 19.93 1.00 k 50.40 499 100.0 249 199.4 100 495.0 49.9 991.0 the ad8426 defaults to g = 1 when no gain resistor is used. the tolerance and gain drift of the r g resistor should be added to the ad8426 specifications to determine the total gain accu- racy of the system. when the gain resistor is not used, gain error and gain drift are minimal.
ad8426 rev. 0 | page 22 of 28 reference terminal the output voltage of the ad8426 is developed with respect to the potential on the reference terminal. this is useful when the output signal needs to be offset to a precise midsupply level. for example, a voltage source can be tied to the ref pin to level- shift the output so that the ad8426 can drive a single-supply adc. the ref pin is protected with esd diodes and should not exceed either +v s or ?v s by more than 0.3 v. for the best performance, source impedance to the ref terminal should be kept below 2 . as shown in figure 62 , the reference terminal, ref, is at one end of a 50 k resistor. additional impedance at the ref terminal adds to this 50 k resistor and results in amplification of the signal connected to the positive input. the amplification from the additional r ref can be computed by 2 (50 k + r ref )/100 k + r ref . only the positive signal path is amplified; the negative path is unaffected. this uneven amplification degrades the cmrr of the amplifier. correct ad8426 op1177 + ? correct ad8426 ad8426 + ? ref ref incorrect v ref v ref v ref ad8426 ref 09490-156 figure 62. driving the reference pin input voltage range the 3-op-amp architecture of the ad8426 applies gain in the first stage before removing common-mode voltage in the difference amplifier stage. in addition, the input transistors in the first stage shift the common-mode voltage up one diode drop. therefore, internal nodes between the first and second stages (node 1 and node 2 in figure 61 ) experience a combina- tion of gained signal, common-mode signal, and a diode drop. this combined signal can be limited by the voltage supplies even when the individual input and output signals are not limited. figure 9 to figure 15 and figure 18 show the allowable common- mode input voltage ranges for various output voltages and supply voltages. equation 1 to equation 3 can be used to understand the inter- action of the gain (g), common-mode input voltage (v cm ), differential input voltage (v diff ), and reference voltage (v ref ). the values for the constants (v ?limit , v +limit , and v ref_limit ) at different temperatures are shown in tabl e 12 . these three equations, along with the input and output voltage range speci- fications in table 2 and tabl e 5 , set the operating boundaries of the part. limit s diff cm vv gv v ? +?> ? 2 (1) limit s diff cm vv gv v + ?+< + 2 (2) ref_limit s ref cm diff vv vv gv ?+< ? ? ? ? ? ? ? ? ? ? ? ? ++ 2 2 (3) table 12. input voltage range constants for various temperatures temperature v ?limit (v) v +limit (v) v ref_limit (v) ?40c ?0.55 +0.8 +1.3 +25c ?0.35 +0.7 +1.15 +85c ?0.15 +0.65 +1.05 +125c ?0.05 +0.6 +0.9 the common-mode input voltage range shifts upward with temp- erature. at cold temperatures, the part requires extra headroom from the positive supply, whereas operation near the negative supply has more margin. conversely, at hot temperatures, the part requires less headroom from the positive supply but is subject to the worst-case conditions for input voltages near the negative supply. a typical part functions up to the boundaries described in this section. however, for best performance, designing with a few hundred millivolts of extra margin is recommended. as signals approach the boundary, internal transistors begin to saturate, which can affect frequency and linearity performance.
ad8426 rev. 0 | page 23 of 28 layout to ensure optimum performance of the ad8426 at the pcb level, care must be taken in the design of the board layout. the ad8426 pins are arranged in a logical manner to aid in this task. 1 2 3 4 12 11 10 9 5678 13141516 ?in1 +in1 rg1 rg1 ad8426 +v s out1 out2 ?v s ?in2 +in2 rg2 rg2 +v s ?v s ref1 ref2 09490-002 figure 63. pinout diagram package considerations the ad8426 is available in a 16-lead, 4 mm 4 mm lfcsp with no exposed paddle. the footprint from another 4 mm 4 mm lfcsp part should not be copied because it may not have the correct lead pitch and lead width dimensions. refer to the outline dimensions section to verify that the corresponding dimensional symbol has the correct dimensions. hidden paddle package the ad8426 is available in an lfcsp package with a hidden paddle. unlike chip scale packages where the pad limits routing capability, this package allows routes and vias directly beneath the chip. in this way, the full space savings of the small lfcsp can be realized. although the package has no metal in the center of the part, the manufacturing process leaves a very small section of exposed metal at each of the package corners, as shown in figure 64 and in figure 73 in the outline dimensions section. this metal is connected to ?v s through the part. because of the possibility of a short, vias should not be placed beneath these exposed metal tabs. 09490-158 hidden paddle exposed metal tabs bottom view notes 1. exposed metal tabs at the four corners of the package are internally connected to ?v s . figure 64. hidden paddle package, bottom view common-mode rejection ratio over frequency poor layout can cause some of the common-mode signals to be converted to differential signals before reaching the in-amp. such conversions occur when one input path has a frequency response that is different from the other. to keep cmrr over frequency high, the input source impedance and capacitance of each path should be closely matched. additional source resistance in the input paths (for example, for input protection) should be placed close to the in-amp inputs to minimize the interaction of the inputs with parasitic capacitance from the pcb traces. parasitic capacitance at the gain setting pins can also affect cmrr over frequency. if the board design has a component at the gain setting pins (for example, a switch or jumper), the component should be chosen so that the para sitic capacitance is as small as possible. power supplies a stable dc voltage should be used to power the instrumenta- tion amplifier. noise on the supply pins can adversely affect performance. see the psrr performance curves in figure 22 and figure 25 for more information. a 0.1 f capacitor should be placed as close as possible to each supply pin. as shown in figure 65 , a 10 f capacitor can be used farther away from the part. in most cases, it can be shared by other precision integrated circuits. ad8426 + v s +in ?in load ref 0.1f 10f 0.1f 10f ?v s out 09490-006 r g figure 65. supply decoupling, ref, and output referred to local ground references the output voltage of the ad8426 is developed with respect to the potential on the reference terminal. care should be taken to tie the refx pins to the appropriate local ground. this should also help minimize crosstalk between the two channels.
ad8426 rev. 0 | page 24 of 28 input bias current return path the other ad8426 terminals should be kept within the supplies. all terminals of the ad8426 are protected against esd. the input bias current of the ad8426 must have a return path to ground. when the source, such as a thermocouple, cannot provide a current return path, one should be created, as shown in figure 66 . for applications where the ad8426 encounters voltages beyond the allowed limits, external current limiting resistors and low leakage diode clamps such as the bav199l, the fjh1100, or the sp720 should be used. thermocouple +v s ref ?v s ad8426 capacitively coupled +v s ref c c ?v s ad8426 transformer +v s ref ?v s ad8426 incorrec t capacitively coupled +v s ref c r r c ?v s ad8426 1 f high-pass = 2 rc thermocouple +v s ref ?v s 10m ? ad8426 transformer +v s ref ?v s ad8426 correct 09490-007 radio frequency interference (rfi) rf interference is often a problem when amplifiers are used in applications where there are strong rf signals. the precision circuits in the ad8426 can rectify the rf signals so that they appear as a dc offset voltage error. to avoid this rectification, place a low-pass rc filter at the input of the instrumentation amplifier (see figure 67 ). the filter limits both the differential and common-mode bandwidth, as shown in the following equations: )2(2 1 c d diff ccr uency filterfreq + = c cm rc uency filterfreq 2 1 = where c d 10 c c . r r ad8426 + v s +in ?in 0.1f 10f 10f 0.1f ref out ?v s r g c d 10nf c c 1nf c c 1nf 4.02k ? 4.02k ? 09490-008 figure 67. rfi suppression figure 66. creating an inpu t bias current return path c d affects the differential signal, and c c affects the common- mode signal. values of r and c c should be chosen to minimize rfi. any mismatch between the r c c at the positive input and the r c c at the negative input degrades the cmrr of the ad8426 . by using a value of c d one order of magnitude larger than c c , the effect of the mismatch is reduced, and performance is improved. input protection the ad8426 has very robust inputs and typically does not need additional input protection. input voltages can be up to 40 v from the opposite supply rail. for example, with a +5 v positive supply and a ?8 v negative supply, the part can safely withstand voltages from ?35 v to +32 v. unlike some other instrumentation amplifiers, the part can handle large differen- tial input voltages even when the part is in high gain. figure 16 , figure 17 , figure 19 , and figure 20 show the behavior of the part under overvoltage conditions.
ad8426 rev. 0 | page 25 of 28 applications information precision strain gage the low offset and high cmrr over frequency of the ad8426 make it an excellent candidate for bridge measurements. the bridge can be connected directly to the inputs of the amplifier (see figure 68 ). 5 v 2.5v 10f 0.1f ad8426 +in ?in r g 350 ? 350 ? 350 ? 350 ? + ? 09490-010 figure 68. precision strain gage differential drive the differential output configuration of the ad8426 has the same excellent dc precision specifications as the single-ended output configuration. differential output using both ad8426 amplifiers the circuit configuration is shown in figure 69 . the differential output specifications in table 2 , table 4 , tabl e 5 , and table 7 refer to this configuration only. the circuit includes an rc filter that maintains the stability of the loop. +in1 ?in1 ad8426 + ? ad8426 + ? 100pf +inx v out? v out+ 10k ? ref2 09490-163 r g figure 69. differential circuit schematic the differential output voltage is set by the following equation: v diff_out = v out+ ? v out? = g (v in+ ? v in? ) where: g r g += k4.49 1 the common-mode output voltage is set by the average of +in2 and ref2. the transfer function is v cm_out = ( v out+ + v out? )/2 = ( v +in2 + v ref2 )/2 a common application sets the common-mode output voltage to the midscale of a differential adc. in this case, the adc reference voltage is sent to the +in2 terminal, and ground is connected to the ref2 terminal. this produces a common- mode output voltage of half the adc reference voltage. 2-channel differential output using a dual op amp another differential output topology is shown in figure 70 . instead of a second in-amp, one-half of a dual op amp creates the inverted output. the recommended dual op amps (the ad8642 and the ad822 ) are packaged in an msop. this configuration allows the creation of a dual-channel, precision differential output in-amp with little board area. figure 70 shows how to configure the ad8426 for differential output. +in ?in ref ad8426 v bias r + ? op amp v out+ v out? r recommended op amps: ad8642, ad822. recommended r values: 5k ? to 20k ? . 09490-009 figure 70. differential output using an op amp the differential output voltage is set by the following equation: v diff_out = v out+ ? v out? = g (v in+ ? v in? ) where: g r g += k4.49 1 the common-mode output voltage is set by the following equation: v cm_out = ( v out+ ? v out? )/2 = v bias the advantage of this circuit is that the dc differential accuracy depends on the ad8426 and not on the op amp or the resistors. this circuit takes advantage of the precise control of the ad8426 over its output voltage relative to the reference voltage. op amp dc performance and resistor matching do affect the dc common- mode output accuracy. however, because common-mode errors are likely to be rejected by the next device in the signal chain, these errors typically have little effect on overall system accuracy. for best ac performance, an op amp with gain bandwidth of at least 2 mhz and a slew rate of at least 1 v/s is recommended. good choices for op amps are the ad8642 and the ad822.
ad8426 rev. 0 | page 26 of 28 tips for best differential output performance keep trace lengths from resistors to the inverting terminal of the op amp as short as possible. excessive capacitance at this node can cause the circuit to be unstable. if capacitance cannot be avoided, use lower value resistors. for best linearity and ac performance, a minimum positive supply voltage (+v s ) is required. table 13 shows the minimum supply voltage required for optimum performance, where v cm_max indicates the maximum common-mode voltage expected at the input of the ad8426. table 13. minimum positive supply voltage temperature equation less than ?10c +v s > (v cm_max + v bias )/2 + 1.4 v ?10c to +25c +v s > (v cm_max + v bias )/2 + 1.25 v more than +25c +v s > (v cm_max + v bias )/2 + 1.1 v driving a cable all cables have a certain capacitance per unit length, which varies widely with cable type. the capacitive load from the cable may cause peaking in the output response of the ad8426 . to reduce the peaking, use a resistor between the ad8426 outputs and the cable (see figure 71 ). because cable capacitance and desired output response vary widely, this resistor is best determined empirically. a good starting point is 50 . ad8426 ad8426 09490-165 differential output single output figure 71. driving a cable the ad8426 operates at such a relatively low frequency that transmission line effects are rarely an issue; therefore, the resistor need not match the characteristic impedance of the cable.
ad8426 rev. 0 | page 27 of 28 driving an adc option 2 shows a circuit for driving higher frequency signals. it uses a precision op amp ( ad8616 ) with relatively high band- width and output drive. this amplifier can drive a resistor and capacitor with a much higher time constant and is, therefore, suited for higher frequency applications. figure 72 shows several different methods of driving an adc. the adc in the aduc7026 microcontroller was chosen for this example because it has an unbuffered, charge sampling architecture that is typical of most modern adcs. this type of architecture typically requires an rc buffer stage between the adc and the amplifier to work correctly. option 3 is useful for applications where the ad8426 must operate from a large voltage supply but drives a single-supply adc. in normal operation, the ad8426 output signal stays within the adc range, and the ad8616 simply buffers the signal. however, in a fault condition, the output of the ad8426 may go outside the supply range of both the ad8616 and the adc. this is not a problem in this circuit, because the 10 k resistor between the two amplifiers limits the current into the ad8616 to a safe level. option 1 shows the minimum configuration required to drive a charge sampling adc. the capacitor provides charge to the adc sampling capacitor, and the resistor shields the ad8426 from the capacitance. to keep the ad8426 stable, the rc time constant of the resistor and capacitor needs to stay above 5 s. this circuit is mainly useful for lower frequency signals. ad8426 ref 100nf 100? 10k ? 10 ? 10nf adc0 adc1 adc2 agnd 3.3v 3.3v 3.3v option 1: driving low frequency signals option 2: driving high frequency signals option 3: protecting adc from large voltages 3.3v ad8426 ad8616 aduc7026 ref 3.3v 10 ? 10nf ad8426 ad8616 ref +15v ?15v av dd 09490-065 figure 72. driving an adc
ad8426 rev. 0 | page 28 of 28 outline dimensions compliant to jedec standards mo-263-vbbc 062309-b 3.75 bcs sq 4.00 bsc sq 0.65 bsc 0.75 0.60 0.50 top view 12 max 0.80 max 0.65 typ seating plane pin 1 indicator coplanarity 0.08 1.00 0.85 0.80 0.35 0.30 0.25 0.05 max 0.02 nom 0.20 ref bottom view 0.60 m a x 0.60 max 1.95 ref sq 1 16 5 8 9 12 13 4 figure 73. 16-lead lead frame chip scale package [lfcsp_vq] 4 mm 4 mm body, very thin quad, with hidden paddle (cp-16-19) dimensions shown in millimeters ordering guide model 1 temperature range package description package option AD8426ACPZ-R7 ?40c to +125c 16-lead lead frame chip scale package [lfcsp_vq] cp-16-19 ad8426acpz-wp ?40c to +125c 16-lead lead frame chip scale package [lfcsp_vq] cp-16-19 ad8426bcpz-r7 ?40c to +125c 16-lead lead frame chip scale package [lfcsp_vq] cp-16-19 ad8426bcpz-wp ?40c to +125c 16-lead lead frame chip scale package [lfcsp_vq] cp-16-19 1 z = rohs compliant part. ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d09490-0-7/11(0)

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